NXP Semiconductors /MIMXRT1011 /AIPSTZ1 /OPACR1

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Interpret as OPACR1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TP0)OPAC150 (TP0)OPAC140 (TP0)OPAC130 (TP0)OPAC120 (TP0)OPAC110 (TP0)OPAC100 (TP0)OPAC90 (TP0)OPAC8

OPAC10=TP0, OPAC13=TP0, OPAC15=TP0, OPAC8=TP0, OPAC12=TP0, OPAC9=TP0, OPAC14=TP0, OPAC11=TP0

Description

Off-Platform Peripheral Access Control Registers

Fields

OPAC15

Off-platform Peripheral Access Control 15

0 (TP0): Accesses from an untrusted master are allowed.

1 (TP1): Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.

OPAC14

Off-platform Peripheral Access Control 14

0 (TP0): Accesses from an untrusted master are allowed.

1 (TP1): Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.

OPAC13

Off-platform Peripheral Access Control 13

0 (TP0): Accesses from an untrusted master are allowed.

1 (TP1): Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.

OPAC12

Off-platform Peripheral Access Control 12

0 (TP0): Accesses from an untrusted master are allowed.

1 (TP1): Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.

OPAC11

Off-platform Peripheral Access Control 11

0 (TP0): Accesses from an untrusted master are allowed.

1 (TP1): Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.

OPAC10

Off-platform Peripheral Access Control 10

0 (TP0): Accesses from an untrusted master are allowed.

1 (TP1): Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.

OPAC9

Off-platform Peripheral Access Control 9

0 (TP0): Accesses from an untrusted master are allowed.

1 (TP1): Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.

OPAC8

Off-platform Peripheral Access Control 8

0 (TP0): Accesses from an untrusted master are allowed.

1 (TP1): Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.

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